Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0)

A Project Funded by National ICT R&D

News and Events

Centre of Excellence in FPGAs/ASIC Research (CEFAR) has been established at NIIT.

The two sub groups of CEFAR are:
1.) Group for Reseach in ASIC/FPGA (GRAF) and
2.) Group for Research in Reconfigurable Architectures for Security in Communication (GRASiC).