Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0)

A project Funded by National ICT R&D

News and Events

Centre of Excellence in FPGAs/ASIC Research (CEFAR) has been established at NIIT.

The two sub groups of CEFAR are:
1.) Group for Reseach in ASIC/FPGA (GRAF) and
2.) Group for Research in Reconfigurable Architectures for Security in Communication (GRASiC).

 

Introduction

The project aims at Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0). The research will be pursued in partnership with Whizz Silicon which is a leading Silicon Valley based technology company delivering best-in-class services for ASICs, FPGAs, and Systems. They offer a full spectrum of design services that enable products from concept to reality for a variety of customers from start-ups to Fortune 500 companies (Intel, AMD etc).
Superspeed Logo
Universal Serial Bus (USB) is used to connect all sorts of devices and is the most successful computer standard in history with billions of units shipped. Current solutions, based on USB 2.0, support transfer rates up to 480 Mb/s but that rate will soon increase tenfold to 4.8Gb/s with the introduction of USB 3.0 enabled products. Over e past several years, there has been a shift in how consumers access and use audio/video media content. Wide use of HD Camcorders, HDTVs, Blue-Ray Disks, and other devices has elevated the need for high-speed data transfer.

The early SuperSpeed (USB 3.0) products will be based on discrete USB 3.0 transceiver/controllers. To bring the cost-effective solution to market, the USB 3.0 functionality would have to be integrated into the devices. This provides new opportunities for producing world-class USB 3.0 IP for SoC/ASIC integration. Most ASICs/SoCs rely on third party IPs for large parts of the total chip functionality.

The research at SEECS plans to develop a suite of low power, configurable and high speed USB 3.0 IP cores including IPs for USB 3.0 host controller, USB 3.0 device controller and USB 3.0 support functions to meet the needs of this "poised-to-explode" market. The figure [Industry timeline for SuperSpeed USB] illustrates the competitive nature of the project. The project speaks volume of the vibrant research culture at NUST SEECS. The project will result in providing research opportunities to students, quality research in a cutting edge field and a breakthrough in the competitive market. 

 

Timeline for SuperSpeed