Publications

 

News and Events

Centre of Excellence in FPGAs/ASIC Research (CEFAR) has been established at NIIT.

The two sub groups of CEFAR are:
1.) Group for Reseach in ASIC/FPGA (GRAF) and
2.) Group for Research in Reconfigurable Architectures for Security in Communication (GRASiC).

  • Book Co-authored

  1. Francisco Rodríguez-Henríquez, Nazar A. Saqib, Arturo Díaz-Pérez, and Cetin Kaya Koc, "Cryptographic Algorithms on Reconfigurable Hardware", ISBN: 0387338837, Springer , Nov 2006.

  • Book Chapter    

  1. Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez, A Generic Coprocessor For Elliptic Curve Scalar Multiplication on Hardware, Embedded Cryptographic Hardware: Design and Security, Chapter 11, ISBN: 1-59454-145-0,Nova Science Publishers New York, 2004.

  • Journals

  1.   Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar A. Saqib and Nareli Cruz-Cortés, "A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm", International Workshop on Applied Reconfigurable Computing ARC 2007, Lecture Notes in Computer Science, Río de Janeiro, Brazil 2007.

  2.   F. Rodríguez-Henríquez, N. A. Saqib , and A. Díaz-Pérez, "4.2 Gbit/s Single-Chip FPGA Implementation of AES Algorithm", in: IEE Electronics Letters, Vol. 39, Springer-Verlag Berlin Heidelberg 2003, 2003, pp. 1115-1116.

  3.   F. Rodríguez-Henríquez, N. A. Saqib , and A. Díaz-Pérez, "A Fast Parallel Implementation of Elliptic Curve Point Multiplication over GF(2m)", Elsevier Journal of Microprocessor and Microsystems 28 (2004) 329-339.

  4.  Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez,  "A Reconfigurable Processor for High Speed Point Multiplication in Elliptic Curves", International Journal of Embedded Systems, Special Issue on Advances in Reconfigurable Architectures, pages 237-249, Volume 1 - Issue 3/4 – 2005.

  5.  Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez, "Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core", FPL 2003, Lecture Notes in Computer Science 2778, pp. 303-312, Springer-Verlag Berlin Heidelberg 2003.

  • Conferences

  1.  Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar A. Saqib and Nareli Cruz-Cortés, " A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm", Lecture Notes in Computer Sciences (LNCS),  Pages 226-237, Volume 4419/2007, June 2007

  2.   Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar A. Saqib and Nareli Cruz-Cortés, "Parallel Itoh-Tsujii multiplicative inversion algorithm for a special class of trinomials", Design, Codes and Cryptography, Pages 19-37, Volume 45, Issue 1, October 2007

  3.  Francisco Rodríguez-Henríquez, Nazar A. Saqib, and Nareli Cruz –Cortez, "A Fast Implementation of Multiplicative Inversion over GF(2m)", ITCC 2005: IEEE Computer Society, pp. 574-579, April 11-13, 2005

  4.   Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez, "Sequential and Pipelined Architecures for AES Implementation", IASTED International Conference on Computer Science and Technology, May 19-21, 2003, Cancun, Mexico, pp. 159-163, IASTED/ACTA Press, 2003.

  5.   Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez, "AES Algorithm Implementation-An efficient Approach for Sequential and Pipeline Architecures", Fourth Mexican International Conference on Computer Science , Sep. 8-12, 2003, Tlaxcala, Mexico, pp. 126-130, IEEE Computer Society Press, 2003.

  6.   Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Perez, "A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2m)", in Proceedings of 18th International Parallel & Distributed Processing Symposium (RAW2004), IEEE Computer Society Press, Santa Fe, New Mexico, p. 144-154.

  7.   Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez," A Parallel Architecture for Computing Scalar Multiplication on Hessian Elliptic Curves", in: International Symposium on Information Technology (ITCC 2004), IEEE Computer Society Press, Las Vegas (NV), USA, 2004, pp. 546-552.

  8.   Arturo Díaz-Pérez, Nazar A. Saqib and, and Francisco Rodríguez-Henríquez, ”Highly Optimized Single-Chip FPGA Implementations of AES Encryption and Decryption Cores”. In: X Workshop IBERCHIP, IWS-2004, 10-12 de Marzo de 2004, Cartagena de Indias, Colombia.

  9.   Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez, "A Compact and Efficient FPGA Implementation of the DES Algorithm", International Conference on Reconfigurable Computing and FPGAs (ReConFig04), Mexican Society for Computer Sciences, Colima, Mexico, 2004.

  10.   A. Díaz-Pérez, N. A. Saqib, F. Rodríguez-Henríquez, "Some Guidelines for Implementing Symmetric-Key Cryptosystems on Reconfigurable-Hardware", IV Jornada de Computación Reconfigurable y Aplicaciones (JCRA), Barcelona, Spain, September 13-15, 2004.